1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, the present invention relates to a frequency generator.
2. Background of the Related Art
FIG. 1 is a block diagram showing a related art clock synthesizer. The related art clock synthesizer includes a quartz crystal oscillator 11, a first frequency divider 13, a phase and frequency detector 15, a low-pass filter 17, a voltage controlled oscillator (VCO) 19 and a second frequency divider 21. The quartz crystal oscillator 11 is connected to the first frequency divider 13. The first frequency divider 13 divides an output frequency of quartz crystal oscillator 11 by a predetermined factor. The second frequency divider 21 divides an output frequency of the VCO 19 by a predetermined factor. The phase and frequency detector 15 receives output signals from each of the first and second frequency dividers 13 and 21 and detects its phase and frequency. The low-pass filter 17 produces an output signal of the phase and frequency detector 15 as a direct current (DC) component signal. The VCO 19 produces a frequency of the output signal of the low-pass filter 17.
In the related art clock synthesizer, a final output value is determined by the output frequency of the first frequency divider 13 and the output frequency of the second frequency divider 21. If the first frequency divider 13 output frequency is faster than the second frequency divider 21 output frequency, the output signal of the phase and frequency detector 15 attains a high level. On the contrary, if the first frequency divider 13 output frequency is slower than the second frequency divider 21 output frequency, the phase and frequency detector 15 output signal attains a low level. If the first frequency divider 13 output frequency is the same as the second frequency divider 21 output frequency, the phase and frequency detector 15 output attains a tri-state.
The output signal of the phase and frequency detector 15 in each of the above cases is input to the low-pass filter 17. The low-pass filter 17 then produces the DC component signal. The DC component signal is input to the VCO 19, and the VCO 19 produces the frequency corresponding to its input signal.
The output frequency of the VCO 19 is again input to the second frequency divider 21. The operation is repeated until the first frequency divider 13 output frequency is the same as the second frequency divider 21 output signal, which is depicted in FIG. 2. If the first frequency oscillator 13 output frequency F1 and the second frequency divider 21 output frequency F2 are initially not the same, the sequence of the above operations is repeatedly executed to obtain the same output frequencies.
However, the related art clock synthesizer has various disadvantages. The sequence of the above operation is executed repeatedly until the frequency lock is realized (i.e., the first frequency divider 13 output frequency is the same as the second frequency divider 19), which is time consuming. Further, in the low-pass filter that is formed by a resistor and a capacitor, the space that the capacitor occupies is too large, and the device size is increased. Thus, the related art clock synthesizer has a disadvantageous layout aspect.